Static memory cell circuit with single bit line and set/reset write function

ABSTRACT

Static memory cell circuits having a single bit line further include first and second word lines, first and second cross-coupled logic gates, and first and second pass gates. The first pass gate is coupled between the bit line and a first storage node at the output of the first logic gate, and has a gate terminal coupled to the first word line. The second pass gate is coupled between the bit line and a second storage node at the output of the second logic gate, and has a gate terminal coupled to the second word line. The bit line and one of the word lines can be used to selectively set or reset a given static memory cell, if desired, without affecting other memory cells along the word line. In some embodiments, the static memory cell is a configuration memory cell of a programmable logic device (PLD).

FIELD OF THE INVENTION

The invention relates to memory cell circuits. More particularly, theinvention relates to a static memory cell circuit that utilizes a singlebit line to perform both set and reset write functions.

BACKGROUND OF THE INVENTION

Programmable logic devices (PLDs) are a well-known type of integratedcircuit that can be programmed to perform specified logic functions. Onetype of PLD, the field programmable gate array (FPGA), typicallyincludes an array of programmable tiles. These programmable tiles caninclude, for example, input/output blocks (IOBs), configurable logicblocks (CLBs), dedicated random access memory blocks (BRAM),multipliers, digital signal processing blocks (DSPs), processors, clockmanagers, delay lock loops (DLLs), and so forth.

Each programmable tile typically includes both programmable interconnectand programmable logic. The programmable interconnect typically includesa large number of interconnect lines of varying lengths interconnectedby programmable interconnect points (PIPs). The programmable logicimplements the logic of a user design using programmable elements thatcan include, for example, function generators, registers, arithmeticlogic, and so forth.

The programmable interconnect and programmable logic are typicallyprogrammed by loading a stream of configuration data into internalconfiguration memory cells that define how the programmable elements areconfigured. The configuration data can be read from memory (e.g., froman external PROM) or written into the FPGA by an external device. Thecollective states of the individual memory cells then determine thefunction of the FPGA.

FIG. 1 is a simplified illustration of an exemplary FPGA. The FPGA ofFIG. 1 includes an array of configurable logic blocks (LBs 101 a–101 i)and programmable input/output blocks (I/Os 102 a–102 d). The LBs and I/Oblocks are interconnected by a programmable interconnect structure thatincludes a large number of interconnect lines 103 interconnected byprogrammable interconnect points (PIPs 104, shown as small circles inFIG. 1). PIPs are often coupled into groups (e.g., group 105) thatimplement multiplexer circuits selecting one of several interconnectlines to provide a signal to a destination interconnect line or logicblock. Some FPGAs also include additional logic blocks with specialpurposes (not shown), e.g., DLLs, RAM, and so forth.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. ACPLD includes two or more “function blocks” connected together and toinput/output (I/O) resources by an interconnect switch matrix. Eachfunction block of the CPLD includes a two-level AND/OR structure similarto those used in Programmable Logic Arrays (PLAs) and Programmable ArrayLogic (PAL) devices. In some CPLDs, configuration data is stored on-chipin non-volatile memory. In other CPLDs, configuration data is storedon-chip in non-volatile memory, then downloaded to volatile memory aspart of an initial configuration sequence.

For all of these programmable logic devices (PLDs), the functionality ofthe device is controlled by data bits provided to the device for thatpurpose. In many PLDs, the data bits are stored in volatile memory(e.g., static memory cells). Some PLDs include millions of these staticmemory cells. Therefore, it is clearly desirable to provide efficientcircuit implementations that enable the reduction in size of staticmemory cells, to reduce the size of the overall PLD or other integratedcircuit (IC) that includes the static memory cells.

One way of reducing the size of the static memory cells in an IC, aswell as the size of the IC, is to use a semiconductor fabricationprocess that allows the use of smaller geometries in the variousfabrication layers. As described in more detail below in conjunctionwith FIGS. 6 and 7, some fabrication processes use an imaging processknown as “alternating aperture phase-shift masking”. Because theseprocesses support the reduction of geometry sizes in PLDs and other ICs,it is clearly desirable to provide methods of implementing static memorycells that comply with the requirements of phase shift masks.

SUMMARY OF THE INVENTION

The invention provides static memory cell circuits having a single bitline. According to one embodiment, a static memory cell includes a bitline, first and second word lines, first and second cross-coupled logicgates, and first and second pass gates. The first pass gate is coupledbetween the bit line and a first storage node at the output of the firstlogic gate, and has a gate terminal coupled to the first word line. Thesecond pass gate is coupled between the bit line and a second storagenode at the output of the second logic gate, and has a gate terminalcoupled to the second word line. The bit line and one of the word linescan be used to selectively set or reset a given static memory cell, ifdesired, without affecting other memory cells along the word line. Insome embodiments, the static memory cell is a configuration memory cellof a PLD, and at least one of the two storage nodes is coupled toprogrammable logic elements within the PLD.

The invention further provides methods of implementing a static memorycell to provide implementations that comply with the requirements ofphase shift masks. According to one embodiment, a phase shift compliantmemory cell is generated by implementing a bit line, first and secondword lines, first and second cross-coupled logic gates, and first andsecond pass gates. The first and second logic gates each have outputterminals coupled to first and second storage nodes, respectively. Thefirst pass gate is coupled between the first storage node and the bitline and has a gate terminal coupled to the first word line. The secondpass gate is coupled between the second storage node and the bit lineand has a gate terminal coupled to the second word line.

The first and second logic gates and the first and second pass gatesinclude transistors that use a fabrication layer (e.g., polysilicon) toimplement a gate node of the transistor. All of these gate nodes extendsubstantially in a first direction (e.g., are generally parallel to oneanother, although some bending of the gate nodes is permissible).Throughout the static memory cell, the fabrication layer used toimplement the gate nodes is implemented without T-shaped polygons incompliance with the requirements for a phase shift mask. In someembodiments, additional fabrication layers (e.g., active diffusionlayers and/or metal layers) are also implemented in compliance with therequirements for phase shift masks.

In some embodiments, the static memory cell is a configuration memorycell for a PLD, and the method includes implementing an interconnectionbetween at least one of the first and second storage nodes and at leastone programmable logic element of the PLD.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the following figures.

FIG. 1 is a simplified diagram of a well known Field Programmable GateArray (FPGA) architecture.

FIG. 2 is a high-level representation of another exemplary FPGA.

FIG. 3 is a schematic diagram illustrating a first well knownconfiguration memory cell for a programmable logic device (PLD).

FIG. 4 is a schematic diagram illustrating a second well known PLDconfiguration memory cell.

FIG. 5 is a schematic diagram illustrating a PLD configuration memorycell according to an embodiment of the present invention.

FIG. 6 illustrates the distribution of light through a traditional maskutilized in a semiconductor fabrication process.

FIG. 7 illustrates the distribution of light through a phase shift maskutilized in a semiconductor fabrication process.

FIG. 8 is a simplified layout diagram for the configuration memory cellof FIG. 3.

FIGS. 9A and 9B are simplified exemplary layout diagrams for theconfiguration memory cell of FIG. 5.

FIG. 10 illustrates the steps of a method of implementing aconfiguration memory cell in a PLD.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth toprovide a more thorough understanding of the present invention. However,it will be apparent to one skilled in the art that the present inventioncan be practiced without these specific details.

As noted above, advanced FPGAs can include several different types ofprogrammable logic blocks in the array. For example, FIG. 2 illustratesan FPGA architecture 200 that includes a large number of differentprogrammable tiles including multi-gigabit transceivers (MGTs 201),configurable logic blocks (CLBs 202), random access memory blocks (BRAMs203), input/output blocks (IOBs 204), configuration and clocking logic(CONFIG/CLOCKS 205), digital signal processing blocks (DSPs 206),specialized input/output blocks (I/O 207) (e.g., configuration ports andclock ports), and other programmable logic 208 such as digital clockmanagers, analog-to-digital converters, system monitoring logic, and soforth. Some FPGAs also include dedicated processor blocks (PROC 210).

In some FPGAs, each programmable tile includes a programmableinterconnect element (INT 211) having standardized connections to andfrom a corresponding interconnect element in each adjacent tile.Therefore, the programmable interconnect elements taken togetherimplement the programmable interconnect structure for the illustratedFPGA. The programmable interconnect element (INT 211) also includes theconnections to and from the programmable logic element within the sametile, as shown by the examples included at the top of FIG. 2.

For example, a CLB 202 can include a configurable logic element (CLE212) that can be programmed to implement user logic plus a singleprogrammable interconnect element (INT 211). A BRAM 203 can include aBRAM logic element (BRL 213) in addition to one or more programmableinterconnect elements. Typically, the number of interconnect elementsincluded in a tile depends on the height of the tile. In the picturedembodiment, a BRAM tile has the same height as four CLBs, but othernumbers (e.g., five) can also be used. A DSP tile 206 can include a DSPlogic element (DSPL 214) in addition to an appropriate number ofprogrammable interconnect elements. An IOB 204 can include, for example,two instances of an input/output logic element (IOL 215) in addition toone instance of the programmable interconnect element (INT 211). As willbe clear to those of skill in the art, the actual I/O pads connected,for example, to the I/O logic element 215 are manufactured using metallayered above the various illustrated logic blocks, and typically arenot confined to the area of the input/output logic element 215.

In the pictured embodiment, a columnar area near the center of the die(shown shaded in FIG. 2) is used for configuration, clock, and othercontrol logic. Horizontal areas 209 extending from this column are usedto distribute the clocks and configuration signals across the breadth ofthe FPGA.

Some FPGAs utilizing the architecture illustrated in FIG. 2 includeadditional logic blocks that disrupt the regular columnar structuremaking up a large part of the FPGA. The additional logic blocks can beprogrammable blocks and/or dedicated logic. For example, the processorblock PROC 210 shown in FIG. 2 spans several columns of CLBs and BRAMs.

Note that FIG. 2 is intended to illustrate only an exemplary FPGAarchitecture. For example, the numbers of logic blocks in a column, therelative width of the columns, the number and order of columns, thetypes of logic blocks included in the columns, the relative sizes of thelogic blocks, and the interconnect/logic implementations included at thetop of FIG. 2 are purely exemplary. For example, in an actual FPGA morethan one adjacent column of CLBs is typically included wherever the CLBsappear, to facilitate the efficient implementation of user logic.

FIG. 3 illustrates a first well-known static memory cell that can beused, for example, to control the programmable elements of an FPGA. Astatic memory cell typically includes two cross-coupled logic gates,such as the two inverters formed by P-channel transistor 301 andN-channel transistor 303, and by P-channel transistor 302 and N-channeltransistor 304. The output nodes of the two cross-coupled logic gatesare referred to herein as “storage nodes”. The storage node of the firstinverter is node QB, and the storage node of the second inverter is nodeQ. In the pictured example, node Q is used to drive programmable passgates 307, part of one or more programmable logic elements in an FPGA.Alternatively, node QB alone or both of nodes Q and QB can be used todrive one or more programmable logic elements.

An N-channel transistor 305 is coupled between node QB and a first bitline BIT, and gated by a word line WORD. Another N-channel transistor306 is coupled between node Q and a second bit line BITB. Transistor 306is also gated by word line WORD. Bit lines BIT and BITB are used tocarry values written to the configuration memory cell, and also to readvalues from the configuration memory cell, e.g., during a configurationreadback procedure.

To perform a write to the memory cell of FIG. 3, a true value is placedon bit line BITB and a complementary value (i.e., the inverse of thetrue value) is placed on bit line BIT. The word line WORD is then drivenhigh. The value from line BIT is placed on node QB, and the value fromline BITB is placed on node Q.

Note that a low value on a bit line can overwrite a high value at astorage node, but a high value on a bit line cannot overwrite a lowvalue at the storage node. This limitation is partially due to thevoltage drop inherent to N-channel transistors passing a high value, andpartially due to the ratio of device sizes between the pass gate and thepulldown on the storage node. Therefore, a single memory cell can bewritten by providing a low value on only one of the bit lines in thememory (i.e., either BIT or BITB of a single row of memory cells), andplacing a high value on only one word line (i.e., only one word lineWORD is high).

To perform a read from the memory cell of FIG. 3, high values are placedon both of bit lines BIT and BITB, and word line WORD is driven high.One of the two nodes Q and QB stores a low value, and will pull thecorresponding bit line down below the value on the other bit line. Thisdifference in values can be detected, e.g., using a sense amplifier, andinterpreted to derive the value stored in the memory cell.

As noted above, a PLD can include literally millions of configurationmemory cells, so it is highly desirable to provide the physicallysmallest memory cell that can fulfill the design requirements. Further,the number of metal lines traversing a memory cell can determine thewidth and/or height of the cell. Note that bit lines BIT and BITB aretypically implemented in metal, because they are used to write to andread from the memory cells. Word lines, on the other hand, can beimplemented in polysilicon, particularly in the configuration memorycells of PLDs. In PLD configuration memory cells, the speed of the readand write processes is not as important, for example, as the speed ofthe read and write processes in the user-operated RAM such as block RAM.Therefore, removing a metal bit line and adding a polysilicon word linecan result in an overall smaller layout without unacceptable loss ofoperating speed.

The configuration memory cell of FIG. 4 provides an implementation inwhich the number of metal lines is reduced by removing one of the twobit lines. The configuration memory cell of FIG. 4 includes the samenumber of transistors as the memory cell of FIG. 3, i.e., two P-channeltransistors 401–402 and four N-channel transistors 403–406. Transistors401 and 403 form a first inverter having a storage node QB. Transistors402 and 404 form a second inverter having a storage node Q. Storage nodeQ drives pass gates 407 as in the circuit of FIG. 3. Pass gate 405couples node QB to the bit line BIT, and is gated by word line WORD.However, pass gate 406 does not couple node Q to a complementary bitline BITB. Instead, pass gate 406 couples node Q to ground GND. Passgate 406 is driven by reset line RESET.

Note that a horizontal bit line BITB has been removed (compared to thecircuit of FIG. 3), and a vertical line RESET has been added. Thevertical line RESET can be implemented in polysilicon, as describedabove. Therefore, the total number of horizontally oriented metal linesthrough the cell has been reduced by one.

To write a high value to the memory cell of FIG. 4 (e.g., to place ahigh value on node Q and a low value on node QB), a low value is placedon bit line BIT and the word line WORD is driven high. The low valuefrom line BIT is placed on node QB, which in turn flips the value atnode Q from low to high. To write a low value to the memory cell (e.g.,to place a low value on node Q and a high value on node QB), signalRESET is driven high. Note that the reset function addresses all cellsalong the RESET line simultaneously.

To perform a read from the memory cell of FIG. 4, bit line BIT is firstpulled high and then tri-stated, and word line WORD is driven high. Alow value at node QB will pull the bit line BIT down to a low value. Ahigh value at node QB leaves the high value on bit line BIT unchanged.The read process is typically slower than the process described for thecircuit of FIG. 3. However, the speed at which PLD configuration memorycells are read is not as important as in some other memory cell arrays.Therefore, this implementation is still suitable for use as a PLDconfiguration memory cell.

FIG. 5 illustrates a static memory cell that is similar in some respectsto the circuit of FIG. 4, but provides for selectively setting orresetting a single memory cell in an array. When the static memory cellis a configuration memory cell for a PLD, the ability to selectively setor reset a single cell can be useful, for example, when performingpartial reconfiguration of the PLD.

The configuration memory cell of FIG. 5 includes the same number oftransistors as the memory cell of FIG. 4, i.e., two P-channeltransistors 501–502 and four N-channel transistors 503–506. Transistors501 and 503 form a first inverter having a storage node QB. Transistors502 and 504 form a second inverter having a storage node Q. Storage nodeQ drives pass gates 507 as in the circuit of FIG. 4. Pass gate 505couples node QB to the bit line BIT. However, pass gate 506 does notcouple node Q to ground or to a second bit line. Instead, pass gate 506couples node Q to the same bit line BIT coupled to pass gate 505. Passgate 505 is driven by set line SET, and pass gate 506 is driven by resetline RESET.

To write a high value to the memory cell of FIG. 5 (e.g., to place ahigh value on node Q and a low value on node QB), a low value is placedon bit line BIT and the set line SET is driven high. The low value fromline BIT is placed on node QB, which in turn flips the value at node Qfrom low to high. To write a low value to the memory cell (e.g., toplace a low value on node Q and a high value on node QB), a low value isplaced on bit line BIT and the reset signal RESET is driven high. Thelow value from line BIT is placed on node Q, which in turn flips thevalue at node QB from low to high.

Note that in the circuit of FIG. 5, the set and reset functions canoptionally be used to directly address a specific memory cell ratherthan a row or a column of memory cells. When the bit line BIT is high,the cells addressed by the bit line will not change state, even if thecorresponding set or reset signal is high. Therefore, to set or resetthe contents of a memory cell, the bit line BIT must be low and eitherthe set line or the reset line must be high. Hence, a specific memorycell can be addressed using one bit line and one set or reset line.

To perform a read from the memory cell of FIG. 5, bit line BIT is firstpulled high and then tri-stated, and either the set line SET or thereset line RESET is driven high. When the SET line is used to performthe read operation, a low value at node QB will pull the bit line BITdown to a low value. A high value at node QB leaves the high value onbit line BIT unchanged. When the RESET line is used to perform the readoperation, a low value at node Q will pull the bit line BIT down to alow value, while a high value at node Q leaves the high value on bitline BIT unchanged. Because of the additional capacitive loading on thebit line compared to the bit line of FIG. 4, the read process for thecircuit of FIG. 5 can be slower than when the circuit of FIG. 4 is used.

The static memory cell of FIG. 5 is particularly well suited to use as aconfiguration memory cell in a PLD, because the read and write speed ofthese cells is not as important as, for example, the read and writespeed of a user RAM array. However, the circuit of FIG. 5 is not limitedto this application, and can be used in any IC that includes staticmemory cells.

FIGS. 6 and 7 illustrate another consideration that can affect thelayout dimensions of structures (including static memory cells) in anintegrated circuit. Minimum feature sizes in semiconductor fabricationprocesses are typically becoming smaller with each successive processgeneration. In optical lithography, the minimum feature size can belimited by the wavelength of the imaging light (among other factors).This limitation can be overcome to some extent by the use of phase shiftmasks, as described by Carcia et al. in an article entitled “Thin Filmsfor Phase-shift Masks”, published by Vacuum and Thin Film, IHSPublishing Group, pp. 14–21, September 1999. (This article is herebyincorporated herein by reference in its entirety.)

FIG. 6 illustrates the behavior of light as it passes through a standardthin-film mask 601. The mask includes a thin film 602 defining apertureswhere the fabrication layer is to be laid down. The imaging light waves603 pass through the mask 601 and are stopped by the thin film 602. Theimaging light reappears through the apertures as emergent light waves604 having the same phase as each other. Waveform 611 illustrates theamplitude of the emergent light waves 604 as they exit the apertures.Waveform 612 illustrates the amplitude of the light waves 604 as theyimpact the wafer (not shown), after random dispersal. Waveform 613illustrates the intensity of the light waves 604 as they impact thewafer.

Note that the light waves from the two apertures overlap and interfereconstructively (i.e., add together at least in part) at the surface ofthe wafer, because the light waves from the two apertures are at leastpartially in phase. Therefore, what was designed to be two separatefeatures on the wafer (defined by the two apertures in mask 601) hasmerged into a single feature. The two apertures in mask 601 are tooclose together to be used in an actual fabrication process.

FIG. 7 illustrates the behavior of light as it passes through analternating aperture phase shift mask 701. The mask 701 includes a thinfilm 702 defining apertures where the fabrication layer is to be laiddown. In addition, covering alternating apertures is a shifter material705 that changes the phase of the emergent light waves 704 by 180degrees.

As in the standard mask of FIG. 6, the imaging light waves 703 passthrough the mask 701 and are stopped by the thin film 702. The imaginglight reappears through the apertures as emergent light waves 704. Lightwaves 704 from alternating apertures are shifted by the shifter material705 and are 180 degrees out of phase from the light waves at neighboringapertures. Waveform 711 illustrates the amplitude of the emergent lightwaves 704 as they exit the apertures. Waveform 712 illustrates theamplitude of the light waves 704 as they impact the wafer (not shown).Waveform 713 illustrates the intensity of the light waves 704 as theyimpact the wafer.

Note that the light waves from the two apertures overlap and interferedestructively (i.e., cancel each other out at least in part in theoverlapping areas) at the surface of the wafer. Therefore, the twofeatures defined by the two apertures in mask 701 remain distinct, andmask 701 could be used in an actual fabrication process. The resolutionof the fabrication process is significantly increased.

A phase shift mask clearly requires that, moving across the mask, areascan be created that are alternately not shifted and phase shifted by 180degrees. For example, it is clear that a “T-shaped” polygon cannot besupported by the process, because at least one of the three areascreated by the “T” must be both phase shifted and not phase shifted.Further, the features implemented by the mask must be laid out generallyparallel to one another, i.e., must extend in substantially the samedirection, although some bending of the features is permissible.

FIG. 8 provides an exemplary memory cell layout in which the polysiliconlayer is not suitable for implementation using a phase shift mask. FIG.8 illustrates a typical layout for the memory cell of FIG. 3. Element801 is an active N+ diffusion layer. Element 802 is an active P+diffusion layer contained within an N-well 803. The areas delineated bydotted lines correspond to a polysilicon fabrication layer. As is wellknown, each intersection of polysilicon and diffusion implements atransistor. P-channel transistors 301 and 302 and N-channel transistors303–306 correspond to similarly labeled transistors in FIG. 3. Labeledcircular areas (Q, QB, GND, VDD, BIT, and BITB indicate contact areasbetween fabrication layers. The metal portions of nodes Q, QB, BIT, andBITB are drawn as simple lines, for clarity. The ground GND and powerhigh VDD interconnections are omitted, for clarity.

Note that the gate nodes of transistors 305–306 are orthogonal to thegate nodes of transistors 301–304. Therefore, the polysilicon layershown in FIG. 8 is not suitable for implementation in a phase shiftmask.

Note that FIGS. 8 and 9A–9B are not intended to describe the exactpolygons that would be used to implement a memory cell, because theexact implementation depends heavily on the design rules specific to aparticular semiconductor foundry and fabrication process. Given thesedesign rules, those of skill in the art can readily produce exact layoutdiagrams conforming to the specified design rules. Therefore, the layoutdiagrams illustrated herein are simplified versions of the actuallayouts, provided to illustrate certain features of the memory cellsdescribed herein.

For example, referring to FIG. 8, note that the word line WORD runsvertically through the memory cell in polysilicon, near the flip linefor the cell. The output of the cell, node Q, exits in polysilicon tothe destination pass transistors 307 from the right side of the figure,on the side opposite the flip line. The BIT and BITB lines (indicated asarrows) run in one of the metal layers in a horizontal direction,orthogonal to the vertically oriented word line WORD.

The memory cell circuit of FIG. 4 is similar to that of FIG. 3, exceptthat the bit line BITB is replaced by a ground line GND. Therefore, thememory cell circuit of FIG. 4 can be laid out, for example, in a similarfashion to that shown in FIG. 8, with the connection to BITB replaced bya connection to ground.

FIGS. 9A and 9B provide exemplary memory cell layouts in which thepolysilicon layer is suitable for implementation using a phase shiftmask. FIGS. 9A and 9B correspond to the memory cell of FIG. 5. Elements901 and 902 are active N+ diffusion layers. Element 903 is an active P+diffusion layer contained within an N-well 904. The areas delineated bydotted lines correspond to a polysilicon fabrication layer. P-channeltransistors 501 and 502 and N-channel transistors 503–506 correspond tosimilarly labeled transistors in FIG. 5. Labeled circular areas (Q, QB,GND, VDD, BIT, SET, and RESET) indicate contact areas betweenfabrication layers. The metal portions of nodes Q, QB, BIT, SET, andRESET are drawn as simple lines, for clarity. The ground GND and powerhigh VDD interconnections are omitted, for clarity.

Note that in both figures, the gate nodes of transistors 505–506 extendin the same direction as the gate nodes of transistors 501–504. Further,the polysilicon layer in FIGS. 9A and 9B is implemented without T-shapedpolygons. Therefore, the polysilicon layer shown in FIGS. 9A and 9Bcomplies with the requirements for a phase shift mask. In someembodiments, other fabrication layers in addition to the polysiliconlayer are implemented without T-shaped polygons. For example, in theembodiment of FIG. 9A the active diffusion layer is also phase-shiftcompliant. In some embodiments, the vertical metal lines are implementedin one metal layer, and the horizontal metal lines are implemented inanother metal layer, and both vertical and horizontal metal lines arephase shift compliant.

In FIG. 9A, the bit line BIT extends in the same direction as the gatenodes of the transistors, and the word lines SET and RESET areorthogonal to the gate nodes. In FIG. 9B, the bit line BIT is orthogonalto the gate nodes, and the word lines SET and RESET extend in the samedirection as the gate nodes.

FIG. 10 illustrates the steps of a method of implementing (e.g.,designing, laying out, or fabricating) a configuration memory cell in aPLD. This method can be applied, for example, to the memory cell circuitillustrated in FIG. 5. However, the method is not limited thereto. Insome embodiments, the method is applied to a PLD that includesprogrammable logic elements.

In step 1001, a bit line is implemented, e.g., utilizing a first metallayer. Note that the nomenclature “first”, “second”, and so forth asused herein is not intended to imply that the designated elements aredesigned, laid out, or fabricated in any particular order. Further, thesteps of the methods shown in FIGS. 10–12 are not necessary performed inthe order shown. For example, the layout process typically involvesentering and altering polygons representing many different layers aspart of an interactive process. Further, the fabrication processtypically does not occur in the illustrated order. For example, metallayers (e.g., bit lines) are typically added after polysilicon layers(e.g., gate nodes).

In step 1002, first and second word lines are implemented, e.g.,utilizing a second metal layer.

In step 1003, first and second cross-coupled logic gates (e.g.,inverters) are implemented. Each of the first and second logic gates hasa storage node (a first and second storage node, respectively) coupledto an output terminal of the logic gate. Each logic gate includes atleast two transistors, and each transistor includes a fabrication layeror “fab. layer” (e.g., polysilicon) that implements the gate of thetransistor, with the gate node extending substantially in a firstdirection.

In step 1004, a first pass gate is implemented between the first storagenode and the bit line implemented in step 1001. The first pass gate hasa gate terminal coupled to the first word line, and utilizes thefabrication layer to implement a gate node thereof that also extendssubstantially in the first direction.

In step 1005, a second pass gate is implemented between the secondstorage node and the bit line implemented in step 1001. The second passgate has a gate terminal coupled to the second word line, and utilizesthe fabrication layer to implement a gate node thereof that also extendssubstantially in the first direction.

In step 1006, an interconnection is implemented between at least one ofthe first and second storage nodes of the configuration memory cell andat least one programmable logic element in the PLD.

In step 1007, which can occur simultaneously and/or interactively atleast with steps 1003–1005, the fabrication layer is laid out throughoutthe configuration memory cell without any T-shaped polygons, incompliance with the requirements for a phase shift mask.

The method illustrated in FIG. 10 (with the exception of step 1006) canalso be applied to ICs other than PLDs, and to a static memory cellother than a configuration memory cell in a PLD or in any other IC.

In some embodiments (e.g., embodiments utilizing current silicon-basedfabrication processes), the fabrication layer used to implement the gatenodes is a polysilicon layer. However, other fabrication processes mayexist or may be developed in which the fabrication layer comprises someother material, and embodiments utilizing these materials are alsoencompassed by the present invention.

In some embodiments, the bit line extends substantially in the firstdirection, i.e., the bit line is traverses the memory cell in adirection generally parallel to the gate nodes, although some bending ispermissible. In some embodiments, the word lines extend substantially ina second direction orthogonal to the first direction. In someembodiments, the bit line extends substantially in the second direction.

Those having skill in the relevant arts of the invention will nowperceive various modifications and additions that can be made as aresult of the disclosure herein. For example, the above text describesthe circuits and methods of the invention in the context of programmablelogic devices (PLDs) such as FPGAs and CPLDs. However, the circuits andmethods of the invention can also be implemented in other integratedcircuits utilizing static memory cells, including non-programmablecircuits.

Further, transistors, P-channel transistors, N-channel transistors,logic gates, inverters, pass gates, memory cells, static memory cells,configuration memory cells, and other components other than thosedescribed herein can be used to implement the various aspects of thepresent invention. Active-high signals can be replaced with active-lowsignals by making straightforward alterations to the circuitry, such asare well known in the art of circuit design. Logical circuits can bereplaced by their logical equivalents by appropriately inverting inputand output signals, as is also well known.

Moreover, some components are shown directly connected to one anotherwhile others are shown connected via intermediate components. In eachinstance the method of interconnection establishes some desiredelectrical communication between two or more circuit nodes. Suchcommunication can often be accomplished using a number of circuitconfigurations, as will be understood by those of skill in the art.

Accordingly, all such modifications and additions are deemed to bewithin the scope of the invention, which is to be limited only by theappended claims and their equivalents.

1. A configuration memory cell for a programmable logic device (PLD)comprising programmable logic elements, the configuration memory cellcomprising: a bit line; first and second word lines; first and secondcross-coupled logic gates having output terminals coupled to first andsecond storage nodes, respectively; a first pass gate coupled betweenthe first storage node and the bit line and having a gate terminalcoupled to the first word line; and a second pass gate coupled betweenthe second storage node and the bit line and having a gate terminalcoupled to the second word line, wherein at least one of the first andsecond storage nodes is coupled to at least one of the programmablelogic elements.
 2. The configuration memory cell of claim 1, wherein thefirst and second logic gates and the first and second pass gates eachcomprise a plurality of transistors, and wherein all of the plurality oftransistors are laid out in a fashion compliant with the requirementsfor a phase shift mask.
 3. The configuration memory cell of claim 2,wherein all of the plurality of transistors are laid out parallel to oneanother.
 4. The configuration memory cell of claim 1, wherein the firstand second logic gates comprise first and second inverters.
 5. Theconfiguration memory cell of claim 1, wherein the first and second passgates comprise N-channel transistors.
 6. The configuration memory cellof claim 1, wherein the programmable logic elements comprise third passgates, and the at least one of the first and second storage nodes iscoupled to gate terminals of the third pass gates.
 7. A programmablelogic device (PLD) comprising a plurality of programmable logic elementsand a plurality of configuration memory cells, each configuration memorycell comprising: a bit line; first and second word lines; first andsecond cross-coupled logic gates having output terminals coupled tofirst and second storage nodes, respectively; a first pass gate coupledbetween the first storage node and the bit line and having a gateterminal coupled to the first word line; and a second pass gate coupledbetween the second storage node and the bit line and having a gateterminal coupled to the second word line, wherein for each configurationmemory cell at least one of the first and second storage nodes iscoupled to at least one of the programmable logic elements.
 8. The PLDof claim 7, wherein the first and second logic gates and the first andsecond pass gates each comprise a plurality of transistors, and whereinall of the plurality of transistors are laid out in a fashion compliantwith the requirements for a phase shift mask.
 9. The PLD of claim 8,wherein all of the plurality of transistors are laid out parallel to oneanother.
 10. The PLD of claim 7, wherein for each configuration memorycell the first and second logic gates comprise first and secondinverters.
 11. The PLD of claim 7, wherein for each configuration memorycell the first and second pass gates comprise N-channel transistors. 12.The PLD of claim 7, wherein the programmable logic elements comprisethird pass gates, and for each configuration memory cell the at leastone of the first and second storage nodes is coupled to gate terminalsof at least one of the third pass gates.
 13. The PLD of claim 7, whereinthe PLD comprises a field programmable gate array (FPGA).
 14. A staticmemory cell, comprising: a bit line; first and second word lines; firstand second cross-coupled logic gates having output terminals coupled tofirst and second storage nodes, respectively; a first pass gate coupledbetween the first storage node and the bit line and having a gateterminal coupled to the first word line; and a second pass gate coupledbetween the second storage node and the bit line and having a gateterminal coupled to the second word line, and wherein the first andsecond logic gates and the first and second pass gates each comprise aplurality of transistors, and wherein all of the plurality oftransistors are laid out in a fashion compliant with the requirementsfor a phase shift mask.
 15. The static memory cell of claim 14, whereinthe first and second logic gates comprise first and second inverters.16. The static memory cell of claim 14, wherein the first and secondpass gates comprise N-channel transistors.
 17. The static memory cell ofclaim 14, wherein all of the plurality of transistors are laid outparallel to one another.
 18. The static memory cell of claim 14, whereinthe static memory cell comprises a configuration memory cell for aprogrammable logic device (PLD).
 19. An integrated circuit (IC)comprising a plurality of static memory cells, each static memory cellcomprising: a bit line; first and second word lines; first and secondcross-coupled logic gates having output terminals coupled to first andsecond storage nodes, respectively; a first pass gate coupled betweenthe first storage node and the bit line and having a gate terminalcoupled to the first word line; and a second pass gate coupled betweenthe second storage node and the bit line and having a gate terminalcoupled to the second word line, and wherein the first and second logicgates and the first and second pass gates each comprise a plurality oftransistors and wherein all of the plurality of transistors are laid outin a fashion compliant with the requirements for a phase shift mask. 20.The IC of claim 19, wherein the IC comprises a programmable logic device(PLD).
 21. The IC of claim 20, wherein the PLD comprises a fieldprogrammable gate array (FPGA).
 22. The IC of claim 19, wherein thefirst and second logic gates comprise first and second inverters. 23.The IC of claim 19, wherein the first and second pass gates compriseN-channel transistors.
 24. The IC of claim 19, wherein all of theplurality of transistors are laid out parallel to one another.